1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory) that carries out a prefetch operation.
2. Description of the Background Art
Among synchronous dynamic random access memories (SDRAM) operating in synchronization with an externally applied clock signal, the SDRAM having data input/output conducted in synchronization with the rising edge and falling edge of an external clock signal is called a double data rate synchronous dynamic random access memory (Double Data Rate SDRAM; referred to as DDR SDRAM hereinafter).
In such a DDR SDRAM, it is postulated that reading out data from a memory cell array conducted at the external clock cycle period is based on a prefetch operation in which a plurality of bits of data are read out to respective output circuits in one read out operation.
The structure and operation of such a DDR SDRAM carrying out a prefetch operation is disclosed in, for example, Japanese Patent Laying-Open No. 8-17184.
The DDR SDRAM that conducts a prefetch operation has a structure in which data of 2N bits are read out at one time from a memory cell array to the output circuit for every one cycle of an external clock. At the output circuit, the 2N bits of data are sequentially set in order to be output for every half cycle of the external clock.
A DDR SDRAM of N=1 is termed “DDR-I” whereas a DDR SDRAM of N=2 is termed “DDR-II”. DDR-I and DDR-II have their specification defined by the JEDEC (Joint Electron Device Engineering Council).
The DDR SDRAM conducting a prefetch operation of 2N data has a chip operating frequency and a data transfer rate per 1 pin that is 2N−1 times the chip operating frequency and 2N times the data transfer rate of a DDR SDRAM that does not conduct a prefetch operation.
Specifically, when one cycle period Tca is 6 ns, an SDR (Single Data Rate) SDRAM that does not conduct a prefetch operation has an operating frequency of 166 MHz and a data transfer rate per 1 pin of 166 MHz.
In contrast, for a DDR SDRAM that conducts a prefetch operation of N=1 (DDR-I), the operating frequency is 166 MHz and the data transfer rate per 1 pin is 333 MHz. A DDR SDRAM (DDR-II) that conducts a prefetch operation of N=2 has an operating frequency of 333 MHz and a data transfer rate of 666 MHz per 1 pin.
However, the problems set forth below are noted in an output circuit that converts parallel data read out simultaneously by the aforementioned prefetch operation sequentially into serial data (parallel/serial conversion: referred to as “P/S conversion” hereinafter).
For example, in the case of a 4-bit prefetch (N=2), 16 selectors will be required per 1 DQ terminal, resulting in increase of the circuit complexity of the output circuit.
Furthermore, the line length in the output circuit will be increased to disable high speed P/S conversion.